The advent of digital technology and the rapid development of microprocessor technology gave rise to a demand for programmable logic. PLDs (“programmable logical devices”) are integrated circuits whose logic function is defined by the user by means of programming. A PLD is a regularly constructed architecture for digital logic operations with a multiplicity of switches that enable a multiplicity of signal paths. The logic function assigned to a PLD in a user-specific fashion is defined by means of the configuration of the PLD.
PLDs include, inter alia, field-programmable gate arrays (FPGA), the functionality of which can be assigned to them by the user, mask-programmable gate arrays (MPGA, also called “structured ASICs”), which can be allocated a logic function by means of hardware configuration. Via-programmable gate arrays (VPGAs) belong among MPGAs.
A digital logic cell maps n input signals onto an output signal. The number of possible mapping functions is 22n. Such a circuit group is realized in accordance with the prior art by using so-called look-up tables (LUT), for example. For this purpose, function values of the logic function are set by means of a data word of 22n bits. In other words, the respectively selected logic function is coded in the data word. The n input signals a0, a1, . . . an-1 are combined with one another in accordance with the selected logic function. Consequently, the logic input signals of the logic function y=f (a0, a1, . . . , an-1) may be regarded as a binary address. The logic input signals are converted into a so-called one-hot coding and a function value is subsequently selected by means of a pass gate logic. A method of this type is known, for example, from Wannemacher, M “Das FPGA-Kochbuch” [“The FPGA cook book”], FIG. 6.4: SRAM cell from XILINX, 1st Edition, International Thomson Publishing Company, Bonn, 1998, p. 111.
In accordance with Wannemacher, M “Das FPGA-Kochbuch” [“The FPGA cook book”], FIG. 7.36: Logic block (CLB) of the XC4000 families, 1st Edition, International Thomson Publishing Company, Bonn, 1998, p. 197, the inputs may serve as control inputs for a multiplexer tree. The multiplexers may be realized in a logic-based manner and/or on the basis of transmission gates.
U.S. Pat. No. 6,529,040 B1 discloses an FPGA on the basis of a look-up table (LUT). In accordance with U.S. Pat. No. 6,529,040 B1, a logic function is only selected by combination of the value of input signals (IN1, IN2, . . . ) with logic selection signals (Q1, Q2 . . . ). To put it another way, in accordance with U.S. Pat. No. 6,529,040 B1, a logic function can be selected by means of applying the input signals and the logic selection signals to transistor inputs of a multiplexer.
The solutions using a look-up table which are disclosed in the prior art have disadvantages with regard to switching speed and/or interference immunity. The known solutions furthermore cannot be realized sufficiently compactly in terms of layout for many applications. Therefore, continued scaling is possible only with difficulty using the LUT solutions disclosed in the prior art.
As an alternative to the known LUT architectures, the prior art discloses interconnections comprising individual logic gates which can be used to construct a desired logic function. However, such an architecture is restricted to the formation of a very specific logic function, whereas the overall scope of all possible logic mapping functions is very complicated to realize using predetermined logic gates. The complicated logic gates are in need of improvement with regard to the achievable switching speed, too. The limitation of the scope of possible logic functions considerably complicates the automatic logic partitioning in the case of an FPGA design.
Furthermore, European Patent Application Publication Number 0 573 175 A2 describes a programmable logic cell having two inputs and six outputs, each of the outputs providing a logic function of the signals present at the two inputs which differs from those at the other outputs. Each output is generated by means of a pair of NMOS field effect transistors, a respective logic function being provided by coupling the gate terminals of the two NMOS field effect transistors to the signals present at the two inputs or their inverted signals, said logic function being selected by means of a 6:1 multiplexer.
U.S. Pat. No. 6,285,218 B1 describes a method and a device for implementing logic using mask-programmable dynamic logic gates.
DE 31 48 410 C2 discloses a programmable combination circuit having a complementarily symmetrical MOS field effect transistor arrangement, network connections of the channels of the MOS field effect transistor pairs being modified by suitably arranged channels of field effect transistors with a programmable threshold voltage, the field effect transistors with a programmable threshold voltage being switched into their conducting or nonconducting state, in a programming step, by application of programming voltages between their gate and channel end. These field effect transistors remain in their conducting or nonconducting state until renewed programming and thus control the logic response behaviour of the combination circuit formed.